1. Technical Field
The present invention relates to memories which have a chip select function, and more particularly, to asynchronous memories which have the chip select function and which utilize address transition detection.
2. Background Art
A chip select function has long been used in memories to disable a memory chip to reduce power consumption. The memory is not responsive to external address signals when deselected by the chip select signal. While there is a power savings, there is also the potential problem of a loss of speed when switching from the deselected mode to the chip selected mode because the circuitry is powered down and there is a necessary recovery time. It is desirable to disable the input stage of as many input signals as is feasible during the deselect mode. In many modern memories, however, address transition is used for equilibrating bit lines as well as for other functions, for the purpose of increasing the speed of operations which is reflected in lower access times. When an access address buffer which receives an external address signal receives a logic low input, the transition from the deselect to select mode will cause the buffer to provide an address transition which is detected as such if the buffer is disabled during the deselect mode. There is then an unnecessary equalization pulse generated as a consequence of the address buffer being disabled during the deselect mode. There is, however, a delay in generating the equalization pulse. The delay is in enabling the address buffer because of an unavoidable delay in responding to the chip select signal. This causes a longer access time for the case in which the memory chip is coming out of the chip select mode than for the case for an address transition during the select mode. The alternative to having the extended access time has been either to not disable the address buffers during the deselect mode and incur the additional power loss, or to put "masking" circuitry in the chip select access path to disable the address transition pulse during the chip select mode of operation.
In asynchronous static random access memories (SRAMs), no external clock signals are provided. This requires an internally generated clock to provide the timing signals for the chip to operate. The clock signals are produced when an input to the RAM (i.e., an address signal) transitions, implying that some externally connected device, such as a microprocessor, desires the chip to perform either a read or write operation based on new input information. However, an SRAM chip also has another input known as a chip select which places the device either in the active addressable state or in an inactive standby state.
Access delay penalties are paid when the asynchronous SRAM comes out of the standby state into the addressable state. If the device generates a clock pulse, then the delay to activate the chip by transitioning to the chip select mode is added to the standard addressable access time.